1. Field of the Invention
The present invention relates to a DC/DC converter, and more particularly, to an input stage circuit of a three-level DC/DC converter.
2. Description of the Related Art
Three-level DC/DC converters with zero-voltage-switching (ZVS) have been adapted for various high-voltage and high-power applications, such as telecommunication systems, battery chargers, and uninterruptible power supply systems. The advantage is low power consumption and high efficiency.
FIG. 1 is a schematic drawing showing a conventional three-level DC/DC converter. The three-level DC/DC converter comprises an input stage circuit 101, a transformer T, and an output stage circuit 102. Wherein the input stage circuit 101 is coupled to the primary side of the transformer T, comprising an input voltage Vin, voltage-dividing capacitors C1 and C2, freewheeling diodes D1 and D2, a flying capacitor C3, metal-oxide-semiconductor filed effect transistors (MOSFETs) Qa, Qb, Qc, and Qd serving as switch apparatuses, and an oscillation inductor Lg. The output stage circuit 102 is coupled to a secondary side of the transformer T, comprising an output rectifying circuit composed of rectifying diodes D3 and D4, and an output filter circuit composed of a filter capacitor Co and a filter inductor Lo.
In the operating theory of the three-level DC/DC converter, these switch apparatuses Qa–Qd are used to control directions of currents flowing through the primary side of the transformer T so that a direct current is converted to an alternating current. Through the output rectifying circuit, an alternating current outputted from the secondary side is converted to a direct current. That's the way the DC/DC converter transforms DC voltage. The turn-on or turn-off states of these MOSFETs Qa–Qd can be controlled by driving signals outputted from phase-shift full bridge control chips (not shown), such as UCC3875 or UCC3895.
Under normal operation, the voltage across the flying capacitor C3 should be maintained at a half of the input voltage Vin. With slight loading or without loading under an open-loop control or close-loop control situation, the voltage across the flying capacitor C3 usually is larger than a half of the input voltage Vin. For example, when the input voltage Vin is 400 V, the voltage across the flying capacitor C3 can reach 250 V.
Under an open-loop control situation, the high voltage across the flying capacitor C3 results from the over—100% phase shift of the driving signal outputted from the control chip as shown in FIG. 2. Wherein, Vgs represents the gate-to-source voltage of the MOSFETs, Vab represents the voltage drop between the points a and b in FIG. 1, ip represents the current flowing through the oscillation inductor Lg shown in FIG. 1, and Vds represents the drain-to-source voltage of the MOSFETs. Referring to FIG. 2, driving signals of the leading bridges Qd and Qc are behind driving signals of the lagging bridges Qa and Qb. Under this circumstance, Qa and Qb become leading bridges. The following is a description of events with respect to several important time periods.
During the period between t0 and t2, the MOSFETs Qa and Qd are turned on and the voltage drop between the points a and b are positive.
During the period between t1 and t2, the MOSFET Qa is turned off before the MOSFET Qd. The primary current of the transformer T flows through the flying capacitor C3 for conversion. The flying capacitor C3 is charged.
During the period between t2 and t3, after the MOSFET Qd is turned off, parasitic capacitors of the MOSFETs Qd and Qa are charged. A parasitic capacitor of the MOSEFT Qc is discharged. The flying capacitor C3 is charged.
During the period between t4 and t5, the sum of the voltage of the MOSFETs Qd and Qa is up to be equal to the input voltage Vin. The voltage across the MOSFETs Qc and Qb are 0. The flying capacitor C3 is charged.
During the period between t5 and t6, the MOSFET Qb is turned on. The current of the transformer T flows to the power source.
After t6, the MOSFET Qc is turned on. The transformer T receives a reverse voltage.
During the conversion, the flying capacitor C3 is always charged and thus has a high voltage. Moreover, the flying capacitor C3 cannot be discharged through the freewheeling diode D1 to the power source.
With light loading or without loading, the high voltage across the flying capacitor C3 results from the unbalance of charging and discharging. FIG. 3A is a configuration showing an equivalent charging circuit of the flying capacitor C3. FIG. 3B is a configuration showing an equivalent discharging circuit of the flying capacitor C3. In FIGS. 3A and 3B, the parameters of these equivalent circuits are different. The parasitic capacitance of the lagging bridge is usually smaller than that of the leading bridge, such that charges received from the charging are more than those lost due to discharging. Accordingly, the voltage across the flying capacitor C3 is undesirably high.
Due to the high voltage across the flying capacitor C3, voltage applied to these MOSFETs becomes unbalanced. Sometimes these MOSFETs would break down and damage the circuits. A solution is using a resistor or a transient voltage suppressor (TVS) connected in parallel to the flying capacitor C3 such that the voltage across the flying capacitor C3 can be maintained at a half of the input voltage Vin. The resistor, however, consumes power, and the value of resistance is hard to be determined. If the resistance is too small or too large, the resistor will adversely affect or even disrupt the operation of the circuit. When using the TVS, the TVS may break down and generate a big surge current when the voltage across the flying capacitor C3 is higher than the suppressing capacity of the TVS. This will undermine the operation of the circuit, and the TVS will completely consume the energy of the discharging.
Accordingly, a better method is desired to solve the issue of the high voltage across the flying capacitor C3 and avoid the disadvantages of the prior technology.